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Barco Silex releases new patent-free and lightweight VC-2 LD video codec at IBC 2015
Louvain-la-Neuve, Belgium – September 8, 2015 -- At IBC 2015 Show in Amsterdam, Barco Silex, the leading provider of video compression IP cores for ASIC and FPGA, announced that the new VC-2 Low Delay codec is now available for licensing to broadcast equipment manufacturers.
The VC-2 Low Delay codec is a patent-free lightweight compression codec ideally suited to encode high-definition video content. VC-2 LD has ultra-low latency and compresses video streams by a compression ratio of 4 times visually lossless.
Originally developed by the BBC Research as Dirac Pro and later standardized as SMPTE 2042, the VC-2 LD codec is patent-free which will facilitate market adoption and interoperability. The SMPTE ST-2047 standard already defines the carriage of high resolution video (up to 1080p60) over HD-SDI using VC-2 LD as a mezzanine compression algorithm. The RTP mapping of the codec is also currently being standardized as an IETF RFC in order to maximize interoperability of the transport over IP networks.
VC-2 Low Delay will enable cost saving associated to the transport of high resolution and high frame rate video content. For example, a 1080p60 stream can be transported over a single 1Gbps Ethernet cable, and up to three 4K/UHD stream at 60 fps can be transported over 10Gbps cable.
“A key distinguishing feature of VC-2 is that it is an open technology designed to avoid patent infringements. So it can be easily included in video production equipment as a hardware or software solution, without the potential costs, uncertainties, and practical difficulties of including other proprietary codecs” says Jean-Marie Cloquet, product manager of the video division at Barco Silex.
Barco Silex will demonstrate the VC2 LD codec on FPGA during IBC show (booth 10.D31a).
Get more information about the VC-2 Low Delay codec at: http://www.barco-silex.com/ip-cores/vc2-codec
Louvain-la-Neuve, Belgium – September 8, 2015 -- At IBC 2015 Show in Amsterdam, Barco Silex, the leading provider of video compression IP cores for ASIC and FPGA, announced that the new VC-2 Low Delay codec is now available for licensing to broadcast equipment manufacturers.
The VC-2 Low Delay codec is a patent-free lightweight compression codec ideally suited to encode high-definition video content. VC-2 LD has ultra-low latency and compresses video streams by a compression ratio of 4 times visually lossless.
Originally developed by the BBC Research as Dirac Pro and later standardized as SMPTE 2042, the VC-2 LD codec is patent-free which will facilitate market adoption and interoperability. The SMPTE ST-2047 standard already defines the carriage of high resolution video (up to 1080p60) over HD-SDI using VC-2 LD as a mezzanine compression algorithm. The RTP mapping of the codec is also currently being standardized as an IETF RFC in order to maximize interoperability of the transport over IP networks.
VC-2 Low Delay will enable cost saving associated to the transport of high resolution and high frame rate video content. For example, a 1080p60 stream can be transported over a single 1Gbps Ethernet cable, and up to three 4K/UHD stream at 60 fps can be transported over 10Gbps cable.
“A key distinguishing feature of VC-2 is that it is an open technology designed to avoid patent infringements. So it can be easily included in video production equipment as a hardware or software solution, without the potential costs, uncertainties, and practical difficulties of including other proprietary codecs” says Jean-Marie Cloquet, product manager of the video division at Barco Silex.
Barco Silex will demonstrate the VC2 LD codec on FPGA during IBC show (booth 10.D31a).
Get more information about the VC-2 Low Delay codec at: http://www.barco-silex.com/ip-cores/vc2-codec